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W83194BR-730
166MHZ CLOCK FOR SIS CHIPSET 1.0 GENERAL DESCRIPTION
The W83194BR-730 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as AMD K7. W83194BR-730 provides 64 CPU/PCI frequencies which are selectable with smooth transitions by hardware or software. W83194BR-730 also provides 13 SDRAM clocks. The W83194BR-730 provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-730 accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at 0~-0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency 2 selection through I C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
* * * * * * * * * * * * * * * * * * Supports AMD CPU with I C. 3 CPU clocks (one free-running CPU clock) 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks 2 AGP clocks 2 REF clocks as 14.318MHz outputs < 250ps skew among CPU and SDRAM clocks < 250ps skew among PCI clocks Skew from CPU(earlier) to PCI clock 1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 66 MHz to 200 MHz CPU Stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio Programmable skew for CPU to SDRAM and CPU to AGP clock outputs 2 2 I C 2-Wire serial interface and I C read back 0.25% or 0~-0.5% spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes MODE pin for power Management and RESET# out when system hang One 48 MHz for USB & one 24_48 MHz for super I/O 48-pin SSOP package
2
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Publication Release Date: Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY 3.0 PIN CONFIGURATION
VddR REF1^/ &AGPSEL REF0^/ &FS3 Vss Xin Xout VddP PCICLK0^/ &FS1 PCICLK1^/ &FS2 PCICLK2^ PCICLK3^ PCICLK4^ PCICLK5/RESET$ Vss VddAGP AGPCLK0/SEL24#_48* AGPCLK1/Mode1* Vss Vss 48MHz/&FS0 24_48MHz/&Mode Vdd48 SDATA* SDCLK* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddLCPU CPUC0$ CPUT0$ CPUCS_C1$ Vss VddSD SDRAM 0 SDRAM 1 SDRAM 2 Vss SDRAM 3 SDRAM 4 SDRAM 5 VddSD SDRAM 6 SDRAM 7 Vss SDRAM 8/PD# SDRAM 9/SDRAM_STOP# VssSD SDRAM 10/PCI_STOP# SDRAM11/CPU_STOP# SDRAM12 VddSD
* : 120K pull-up &: 120K pull-down ^ : 2X driving stength $ : Open-drain #: Active LOW
4.0 PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up
4.1 Crystal I/O
SYMBOL Xin Xout PIN 5 6 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
4.2 CPU, SDRAM, PCI, AGP Clock Outputs
SYMBOL CPUC0$ CPUT0$ CPUCS_C1$ PIN 47,46 I/O OD FUNCTION Open drain output clock for host frequencies CPU. Powered by VddLCPU. Stopped if CPU_STOP# is low. Open drain clock for chipset. Stopped if CPU_STOP# is low and Register1 bit7=0. The same phase as CPUC0$. SDRAM clock outputs. The same phase as CPUC0$ Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, PD# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, SDRAM_STOP# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, PCI_STOP# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, CPU_STOP# input Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched Input. PCI clock during normal operation. (pin 17 MODE1=1) If pin17 MODE1=0, RESET# (open drain, 4ms low active pulse when Watch Dog time out) Low skew (< 250ps) AGP clock output. Latched Input. SEL24#_48*=1, Pin 21 is 24MHz; SEL24_48*=0, Pin21 is 48MHz AGP clock outputs Latched Input. Mode1*=1, Pin 13 is PCICLK; Mode1*=0, Pin13 is RESET#
45
OD
SDRAM [ 0:7],12 SDRAM 8/PD# SDRAM9/ SDRAM_STOP# SDRAM 10/ PCI_STOP# SDRAM 11/ CPU_STOP# PCICLK0^/&FS1
42,41,40,38,37 ,36,34,33, 26 31 30 28 27 8
OUT OUT OUT OUT OUT I/O
PCICLK1^/&FS2
9
I/O
PCICLK [2:4]^ PCICLK5/ RESET$ AGPCLK0/ SEL24#_48* AGPCLK1/ Mode1*
10,11,12 13
I/O I/O
16
I/O
17
OUT
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
4.3 I2C Control Interface
SYMBOL SDATA* SDCLK* PIN 23 24 I/O I/O IN
2 2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I C 2-wire control interface
4.4 Fixed Frequency Outputs
SYMBOL REF0 ^/ &AGPSEL PIN 2 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the atched input for &AGPSEL at initial power up for H/W selecting the output frequency of AGP clocks. 14.318MHz reference clock. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24_48MHz / &Mode 21 I/O 24_48MHz output clock, selected by pin16. Latched Input. &Mode=0, Pin 27,28,30,31 are SDRAM clocks; &Mode=0, Pin27,28,29,31 areCPU_STOP#, SDRAM_STOP#, PCI_STOP#,PD# 48MHz / &FS0 20 I/O 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.
REF1 ^/ &FS3
3
I/O
4.5 Power Pins
SYMBOL VddR VddAGP VddLCPU VddP VddSD Vdd48 Vss PIN 1 15 48 7 43,35,29,25 19 FUNCTION Power supply for Ref [0:1] crystal and core logic. Power supply for AGP output, 3.3V. Power supply for CPUC0,T0,CS_C1, either 2.5V or 3.3V. Power supply for PCICLK[0:5], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. Power for 24 & 48MHz output buffers and fixed PLL core.
4,14,18,19,29,32,39,4 Circuit Ground. 4
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY 5.0 FREQUENCY SELECTION BY HARDWARE
FS3 FS2 FS1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO (MHz) 400 400 300 400 336 500 372 400 400 300 333 330 332 360 192 192 CPU (MHz) 100 100 100 100 112 125 124 133 133 150 111 110 166 90 48 45 SDRAM (MHz) 100 133 150 66.6 112 100 124 100 133 150 166 165 166 90 48 60 PCI (MHz) 33.3 33.3 30.0 33.3 33.6 31.3 31 33.3 33.3 30 33.3 33.0 33.3 30 32 30 AGPSEL=0 (MHz) 66.6 66.6 60 66.6 67.2 62.5 62 66.6 66.6 60 66.6 66 66.6 60 64 60 AGPSEL=1 (MHz) 50 50 50 50 56 50 46.5 50 50 50 55.6 55 55.6 45 48 45
6.0 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
Bytes sequence order for I C controller :
Clock Address A(6:0) & R/W
2
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when Read back", the data sequence is as follows :
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY FREQUENCY BY SOFTWARE
VCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 400 400 300 400 336 500 372 400 400 300 333 330 332 360 192 192 368 380 384 392 368 380 384 392 354 360 366 378 378 384 390 408 CPU 100 100 100 100 112 125 124 133 133 150 111 110 166 90 48 45 92 95 96 98 92 95 96 98 118 120 122 126 126 128 130 136 SDRAM (MHz) 100 133 150 66.6 112 100 124 100 133 150 166 165 166 90 48 60 92 95 96 98 122.67 126.67 128 130.67 88.5 90 91.5 94.5 126 128 130 136 PCI (MHz) 33.3 33.3 30.0 33.3 33.6 31.3 31 33.3 33.3 30 33.3 33.0 33.3 30 32 30 30.67 31.67 32 32.67 30.67 31.67 32 32.67 29.5 30 30.5 31.5 31.5 32 32.5 34 AGPSEL=0 AGPSEL=1 (MHz) 66.6 66.6 60 66.6 67.2 62.5 62 66.6 66.6 60 66.6 66 66.6 60 64 60 61.33 63.33 64 65.33 61.33 63.33 64 65.33 59 60 61 63 63 64 65 68 (MHz) 50 50 50 50 56 50 46.5 50 50 50 55.6 55 55.6 45 48 45 46 47.5 48 49 46 47.5 48 49 44.25 45 45.75 47.25 47.25 48 48.75 51 SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 (MHz) (MHz)
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
VCO CPU SDRAM PCI AGPSEL=0 AGPSEL=1 SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 408 412 416 420 408 412 416 424 390 405 414 426 411 414 417 429 429 432 435 438 441 444 456 459 468 474 480 489 498 525 534 540 102 103 104 105 102 103 104 106 130 135 138 142 137 138 139 143 143 144 145 146 147 148 152 153 156 158 160 163 166 175 178 180 102 103 104 105 136 137.33 138.67 141.33 97.5 101.25 103.5 106.5 137 138 139 143 107.25 108 108.75 109.5 110.25 111 114 114.75 117 118.5 120 122.25 124.5 131.25 133.5 135 34 34.33 34.67 35 34 34.33 34.67 35.33 32.5 33.75 34.5 35.5 34.25 34.5 34.75 35.75 35.75 36 36.25 36.5 29.4 29.6 30.4 30.6 31.2 31.6 32 32.6 33.2 35 35.6 36 68 68.67 69.33 70 68 68.67 69.33 70.67 65 67.5 69 71 68.5 69 69.5 71.5 71.5 54 54.38 54.75 55.13 55.5 57 57.38 58.5 59.25 60 61.13 62.25 65.63 66.75 67.5 51 51.5 52 52.5 51 51.5 52 53 48.75 50.63 51.75 53.25 51.38 51.75 52.13 53.63 53.63 43.2 43.5 43.8 44.1 44.4 45.6 45.9 46.8 47.4 48 48.9 49.8 52.5 53.4 54
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
5.1 Register 0: Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 2 SSEL5 ( Frequency table selection by software via I C) 2 SSEL4 ( Frequency table selection by software via I C) 2 SSEL3 ( Frequency table selection by software via I C) 2 SSEL2 ( Frequency table selection by software via I C) 2 SSEL1 ( Frequency table selection by software via I C) 2 SSEL0 (Frequency table selection by software via I C ) 0 = Selection by hardware 2 1 = Selection by software I C - Bit (7:2) 0 = Running 1 = Tristate all outputs
5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 0 0 1 1 1 1 Pin 27 26 45 46 47 Description CPUCS_C1$ free running control 1: stopped by CPU_STOP# 0: Free running pin SDRAM11 (Active / Inactive) 0 = Normal 1 = Spread spectrum enable 0 = 0.25% Center type Spread Spectrum Modulation 1= 0 ~ (-0.5%) Down type Spread Spectrum Modulation SDRAM12 (Active / Inactive) CPUCS_C1$(Active / Inactive) CPUC0$ (Active / Inactive) CPUT0$ (Active / Inactive)
5.3 Register 2: PCI, AGP Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 17 16 13 12 11 10 9 8 Description AGPCLK1(Active / Inactive) AGPCLK0(Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive)
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
5.4 Register 3: SDRAM Clock Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 33 34 36 37 38 40 41 42 Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive)
5.5 Register 4: SDRAM Clock Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X X X X X 1 1 1 Pin 28 30 31 AGPSEL# FS3# FS2# FS1# FS0# SDRAM10 (Active / Inactive) SDRAM9 (Active / Inactive) SDRAM8 (Active / Inactive) Description
5.6 Register 5: Skew Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin 21 20 Description CSkew2 (SDRAM to CPU skew program bit) CSkew1 (SDRAM to CPU skew program bit) CSkew0 (SDRAM to CPU skew program bit) CAkew2 (AGP to CPU skew program bit) CAkew1 (AGP to CPU skew program bit) CAkew0 (AGP to CPU skew program bit) 24_48MHz(Active / Inactive) 48MHz(Active / Inactive)
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY 5.7 Register 6: Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 X 0 0 0 0 0 0 Pin Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0 Enable Count
5.8 Register 7: M/N Program Register and Divisor
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 0 0 0 0 0 Pin N value bit 8 Test 1 (Internal test use) Test 0 (Internal test use) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 Description
5.9 Register 8: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 Description
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY 5.10 Register 9: Spread Spectrum Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 Description
5.11 Register 10: Divisor Register
Bit 7 @PowerUp 0 Pin Description 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M Ratio SEL3 (See ratio selection table) Ratio SEL2 (See ratio selection table) Ratio SEL1 (See ratio selection table) Ratio SEL0 (See ratio selection table) AGP Ratio SEL2 (See ratio selection table1) AGP Ratio SEL1 (See ratio selection table1) AGP Ratio SEL0 (See ratio selection table1)
6 5 4 3 2 1 0
X X X X X X X
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5.12 Register 11: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 1 0 1 Pin Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY 5.13 Register 12: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 1 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Version ID Version ID Version ID Version ID Description
Ratio Selection Table Reg10 Reg10 Reg10 Reg10 VCO/ VCO/ VCO/ bit6 bit5 bit4 bit3 CPU SDRAM PCI SSEL3 SSEL2 SSEL1 SSEL0 ratio ratio ratio 0 0 0 0 2 2 10 0 0 0 1 2 3 10 0 0 1 0 3 2 10 0 0 1 1 3 3 10 0 1 0 0 3 3 12 0 1 0 1 3 3 16 0 1 1 0 3 4 12 0 1 1 1 3 4 16 1 0 0 0 4 3 10 1 0 0 1 4 3 12 1 0 1 0 4 3 16 1 0 1 1 4 4 12 1 1 0 0 4 6 12 1 1 0 1 6 3 12 1 1 1 0 6 4 12 1 1 1 1 6 6 12
Ratio Selection Table 1 Reg10 Reg10 Reg10 bit2 bit1 bit0 VCO/AGP ratio 3 5 6 8 4 10
AGP2 AGP1 AGP0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY
ORDERING INFORMATION
Part Number W83194BR-730 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
HOW TO READ THE TOP MARKING
W83194BR-730 28051234 002GAB
1st line: Winbond logo and the type number: W83194BR-730 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 002: packages made in '00, week 02 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date:Oct. 2000 Revision 0.60
W83194BR-730
PRELIMINARY PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date:Oct. 2000 Revision 0.60

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